1. Field of the Invention
The present invention relates to semiconductor memory devices. More particularly, the invention relates to semiconductor memory devices capable of arbitrarily setting the number of memory cells to be tested during a parallel bit test (PBT) and a related test method.
This application claims the benefit of Korean Patent Application No. 10-2006-0064464, filed on Jul. 10, 2006, the subject matter of which is hereby incorporated by reference.
2. Description of the Related Art
Synchronous semiconductor memory devices include a plurality of memory cells arranged in a matrix. A defective memory cell among this plurality of memory cells can cause problems during operation of a system incorporating the constituent memory device.
As the integration density and operating speed of synchronous memory devices increases, the ability to detect and correct defective memory cells during ever more efficient test procedures become increasingly important. Accordingly, numerous types of test procedures adapted to detect and/or correct defective memory cells have been developed.
FIG. 1 illustrates an exemplary configuration for a conventional semiconductor memory device 10 capable of undergoing a parallel bit test (PBT). Referring to FIG. 1, semiconductor memory device 10 performs the PBT on four bits of cell data—D0, D1, D2 and D3. Semiconductor memory device 10 accordingly includes a circuit designed to facilitate this 4-bit test mode. In the illustrated embodiment, cell data D0, D1, D2 and D3 are assumed to have values of “1”, “0”, “1” and “0”, respectively.
Semiconductor memory device 10 includes first, second and third comparators; FCOMP0, FCOMP1 and SCOMP0. The first comparator FCOMP0 compares the first cell data D0 to the third cell data D2, and the second comparator FCOMP1 compares the second cell data D1 to the fourth cell data D3.
The first, second and third comparators FCOMP0, FCOMP1 and SCOMP0 respectively execute an exclusive-OR operation. Accordingly, the first comparator FCOMP0 outputs “PASS” as a comparison result when the first cell data D0 and the third cell data D2 have the same value and outputs “FAIL” as a comparison result when the first cell data D0 and the third cell data D2 respectively have different values. The second comparator FCOMP1 outputs “PASS” when the second cell data D1 and the fourth cell data D3 have the same value and outputs “FAIL” when the second cell data D1 and the fourth cell data D3 respectively have different values,
The third comparator SCOMP0 compares the output signal of the first comparator FCOMP0 to the output signal of the second comparator FCOMP1. The third comparator SCOMP0 outputs “PASS” when the output signals of the first and second comparators FCOMP0 and FCOMP1 are identical to each other and outputs “FAIL” when the output signals of the first and second comparators FCOMP0 and FCOMP1 are different from each other. When the third comparator SCOMP0 outputs “PASS”, the result of the PBT performed on the four cell data D0, D1, D2 and D3 is determined to be acceptable (i.e., a “PASS” value is output).
In the illustrated example, it is assumed that a memory cell storing the first cell data D0 is defective. That is, the first cell data D0 is “1” when the corresponding input to semiconductor memory device 10 should have resulted in stored “0”. Such a failure may be generated when stray electrical current from neighboring memory cells changes the stored data value. Accordingly, the first comparator FCOMP1 compares the first cell data D0 having a value “0” to the third cell data D2 having a value “1”. As a result, the first comparator FCOMP0 outputs “FAIL”.
The third comparator SCOMP0 outputs “FAIL” because the output signals of the first and second comparators FCOMP0 and FCOMP1 are different from each other irrespective of whether memory cells storing the other cell data D1, D2 and D3 are defective or not. Accordingly, the PBT result relative to all four cell data D0, D1, D2 and D3 is determined to be unacceptable (i.e. a “FAIL” value is output).
In this context, conventional semiconductor memory devices perform parallel bit testing on a fixed minimum grouping of cell data. The corresponding test circuitry is defined in relation to this cell data grouping. Once defined, the amount of cell data being tested is restricted by the particular design of test circuitry and selected data input to the test circuitry.
For example, when the four cell output data D0, D1, D2 and D3 are tested using the circuitry illustrated in semiconductor memory device of FIG. 1, the four cell data may only have acceptable values of “0000”, “01011”, “1010”, and “1111”. Individual memory cells may not be tested outside this group of acceptable data values. Thus, if one or more memory cells generates erroneous data, the memory cell paired with the defective memory cell may not be effectively tested because the PBT circuitry is too rigid in its application.